In the field of electronics, a collection of wires or lines which connect several electronic devices is called a bus. Because a bus can effectively be shared by multiple devices, modern computer systems may incorporate one or more bus systems for the communication of data between devices. Such bus systems can be synchronous or asynchronous. A synchronous bus system utilizes a clock signal to time the transfer of data. In contrast, an asynchronous bus system does not utilize a clock signal for the transfer of data.
In general, synchronous bus systems allow data to be transferred more rapidly than asynchronous bus systems. Consequently, synchronous bus systems are widely used for high-speed devices (e.g., memory, hard disk drive, video controller, etc.), whereas asynchronous bus systems are preferred for low-speed devices (e.g., mouse, keyboard, etc.).
A significant problem with synchronous bus systems, however, is clock-data skew. Clock-data skew is a delay between a data signal and the clock signal used to time the transfer data carried by the data signal. Clock-data skew is caused mainly by a mismatch between a transmission line for the clock signal and the transmission lines of the data I/O buses. This mismatch may be attributable to differences in length, impedance, or other variables. In high-speed computer systems, the amount of clock-data skew may exceed the period of a clock cycle, in which case, the transfer of data becomes more complicated and difficult if a synchronous bus system is used.
A number of previously developed techniques have attempted to solve the problem of clock-data skew in a synchronous bus system. One previously developed technique limits the length of the clock line and the data bus so that clock-data skew cannot become very large. This is impractical, however, because modern computer systems require clock lines and data buses with relatively long lengths in order to support extensibility.
Another previously developed technique uses a plurality of clock sources within a bus system. Each clock source generates a respective clock signal which is output on its own clock line. Each clock line is connected to a separate device. In order to provide a reference clock with the same phase for all devices in the bus system, the clock lines must be matched so that the respective clock signals are synchronously received at the devices. A disadvantage of this previously developed technique for a bus system is its relative complexity. Because all clock lines must be perfectly matched, the system cannot be easily implemented in practice. Another disadvantage of the technique is that the operating frequency of the bus system depends on the propagation delay of the data bus. As the length of the data bus is extended, the system operation frequency must be slowed.
With yet another previously developed technique for a synchronous bus system, the clock line, all data buses, and all control buses must be perfectly matched. With this arrangement, all data and control signals travel on the respective buses in a constant phase relationship with respect to the clock signal. Accordingly, clock-data skew is reduced. A disadvantage of this previously developed technique is the requirement that all signals be perfectly matched. More specifically, in a printed circuit board (PCB) design, it is very difficult to match all signals due to various uncontrollable factors, such as variation in the length and width of the bus, mismatch of material characteristics, and corner effects of the bus.